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1. general description the PTN3381B is a high-speed level shifter device which converts four lanes of low-swing ac-coupled differential input signals to dvi v1.0 and hdmi v1.3a compliant open-drain current-steering differential output signals, up to 1.65 gbit/s per lane. each of these lanes provides a level-shifting differential buffer to translate from low-swing ac-coupled differential signaling on the source side, to tmds-type dc-coupled differential current-mode signaling terminated into 50 to 3.3 v on the sink side. additionally, the PTN3381B provides a single-ended active buffer for voltage translation of the hpd signal from 5 v on the sink side to 3.3 v on the so urce side and provides a channel with active buffering and level shifting of the ddc channel (consisting of a clock and a data line) between 3.3 v source-side and 5 v sink-sid e. the ddc channel is implemented using active i 2 c-bus buffer technology providing capaciti ve isolation, redriving and level shifting as well as disablement (isolation between so urce and sink) of the clock and data lines. to provide the highest level of integration in external adapter (or: dongle) applications, PTN3381B includes an onboard 5 v dc regulator. its output is designed to provide the required 5 v power supply to the dvi or hdmi connector, thereby eliminating the need for a separate external regulator. the on-board regulator needs only two external capacitors to operate, and its output is active whenever a valid 3.3 v is applied to the PTN3381B v dd pins. the low-swing ac-coupled differential input signals to the PTN3381B typically come from a display source with multi-mo de i/o, which supports multiple display standards, e.g., displayport, hdmi and dvi. while the input differential signals are configured to carry dvi or hdmi coded data, they do not comply with the electrical requirements of the dvi v1.0 or hdmi v1.3a specification. by using PTN3381B, chip set vendors are able to implement such reconfigurable i/o s on multi-mode display source devices, allowing the support of multiple display standards wh ile keeping the number of chip set i/o pins low. see figure 1 . the PTN3381B main high-speed differential lanes feature low-swing self-biasing differential inputs which are compliant to the electrical specifications of displayport standard v1.1 and/or pci express standard v1.1 , and open-drain current-steering differential outputs compliant to dvi v1.0 and hdmi v1.3a electrical specifications. the i 2 c-bus channel actively buffers as well as level-translates the ddc signals for optimal capacitive isolation. its i 2 c-bus control block also provides for optional software hdmi dongle detect by issuing a predetermined code sequence upon a read command to an i 2 c-bus specified address. the PTN3381B also supports power-saving modes in order to minimize current consumption when no display is active or connected. the PTN3381B is a fully featured hdmi as we ll as dvi level shifter. it is functionally equivalent to ptn3361b but provides an onboard 5 v regulator. PTN3381B enhanced performance hdmi/dvi level shifter with voltage regulator, dongle detect su pport and activ e ddc buffer rev. 2 ? 15 october 2010 product data sheet
PTN3381B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 15 october 2010 2 of 30 nxp semiconductors PTN3381B fully integrated hdmi/dvi level shifter PTN3381B is powered from a single 3.3 v power supply consuming a small amount of power (100 mw typical without load at 5 v regu lator output) and is offered in a 48-terminal hvqfn48 package. remark: tmds clock and data lanes can be assigned ar bitrarily and interchangeably to d[4:1]. fig 1. typical application system diagram 002aae07 6 out_d1 ? out_d1+ in_d1 ? in_d1+ hpd_source hpd_sink scl_sink sda_sink ddc_en (0 v to 3.3 v) scl_source sda_source out_d2 ? out_d2+ in_d2 ? in_d2+ out_d3 ? out_d3+ in_d3 ? in_d3+ out_d4 ? out_d4+ in_d4 ? in_d4+ PTN3381B oe_n dvi/hdmi connector 5 v 5 v 0 v to 5 v 0 v to 3.3 v 3.3 v 3.3 v 3.3 v ac-coupled differential pair clock clock lane data lane data lane data lane ac-coupled differential pair tmds data ac-coupled differential pair tmds data ac-coupled differential pair tmds data tx tx ff tmds clock pattern multi-mode display source tx tx ff tmds coded data tx tx ff tmds coded data tx tx ff tmds coded data pcie phy electrical configuration ddc i/o (i 2 c-bus) pcie output buffer reconfigurable i/os pcie output buffer pcie output buffer pcie output buffer v5out 5 v dc out ddet 3.3 v
PTN3381B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 15 october 2010 3 of 30 nxp semiconductors PTN3381B fully integrated hdmi/dvi level shifter 2. features and benefits 2.1 high-speed tmds level shifting ? converts four lanes of low-swing ac-coupled differential input signals to dvi v1.0 and hdmi v1.3a compliant open-drain current-steering differential output signals ? pin-programmable pre-emphasis feature ? tmds level shifting operation up to 1.65 gbit/s per lane (165 mhz character clock) ? tmds level shifting operation up to 2.25 gbit/s per lane (225 mhz character clock) using pre-emphasis feature ? integrated 50 termination resistors for self -biasing differential inputs ? back-current safe outputs to disallow current when device power is off and monitor is on ? disable feature to turn off tmds inputs and outputs and to enter low-power state 2.2 ddc level shifting ? integrated ddc buffering and level shifting (3.3 v source to 5 v sink side) ? rise time accelerator on sink-side ddc ports ? 0hz to 400khz i 2 c-bus clock frequency ? back-power safe sink-side term inals to disallow backdrive cu rrent when power is off or when ddc is not enabled 2.3 hdmi dongle detect support ? incorporates i 2 c slave rom ? responds to ddc read to address 81h with predetermined byte sequence ? feature enabled by pin ddet (must be enabled for correct operation in accordance with displayport intero perability guideline) 2.4 hpd level shifting ? hpd non-inverting level shift from 0 v on the sink side to 0 v on the source side, or from 5 v on the sink side to 3.3 v on the source side ? integrated 200 k pull-down resistor on hpd sink input guarantees ?input low? when no display is plugged in ? back-power safe design on hpd_sink to disallow backdr ive current when power is off 2.5 5 v dc voltage regulator ? generates 5 v for the dvi/hdmi connector from the 3.3 v dp_pwr pin supplied by the displayport connector ? supports up to 75 ma of load current with an accuracy of 300 mv ? only two external capacitors required ? eliminates need for an external 5 v regulator in dongle applications ? back drive protection on 5 v output ? short-circuit protection ? overcurrent protection
PTN3381B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 15 october 2010 4 of 30 nxp semiconductors PTN3381B fully integrated hdmi/dvi level shifter 2.6 general ? power supply 3.3 v 10 % ? esd resilience to 4 kv hbm, 1 kv cdm ? support for optional hdmi dongle detection via ddc/i 2 c-bus channel ? power-saving modes (using output enable) ? back-current-safe design on all sink-s ide main link, ddc and hpd terminals ? transparent operation: no re-timing or software configuration required 3. applications ? displayport to hdmi adapters ? displayport to dvi adapters required to drive long cables 4. ordering information table 1. ordering information type number package name description version PTN3381Bbs hvqfn48 plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 7 7 0.85 mm sot619-1
PTN3381B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 15 october 2010 5 of 30 nxp semiconductors PTN3381B fully integrated hdmi/dvi level shifter 5. functional diagram fig 2. functional diagram of PTN3381B 002aae077 out_d1 ? out_d1+ input bias 50 50 in_d1 ? in_d1+ hpd level shifter hpd_source (0 v to 3.3 v) hpd_sink (0 v to 5 v) 200 k scl_sink sda_sink ddc_en (0 v to 3.3 v) scl_source sda_source out_d2 ? out_d2+ in_d2 ? in_d2+ out_d3 ? out_d3+ in_d3 ? in_d3+ out_d4 ? out_d4+ in_d4 ? in_d4+ PTN3381B oe_n enable enable enable enable input bias 50 50 input bias 50 50 input bias 50 50 enable enable enable enable ddc buffer and level shifter i 2 c-bus slave rom ddet dc regulator v5out cp cn c reg(ext) c o(reg)
PTN3381B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 15 october 2010 6 of 30 nxp semiconductors PTN3381B fully integrated hdmi/dvi level shifter 6. pinning information 6.1 pinning 6.2 pin description hvqfn48 package supply ground is connected to both gnd pins and expos ed center pad. gnd pins and the exposed center pad must be connect ed to supply ground for proper device operation. for enhanced thermal, electrical, and board leve l performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the pcb in the thermal pad region. fig 3. pin configuration for hvqfn48 out_d4+ out_d4 ? v dd out_d3+ out_d3 ? gnd out_d2+ out_d2 ? v dd out_d1+ out_d1 ? gnd oe_n v dd gnd scl_sink sda_sink hpd_sink gnd ddc_en v dd v5out cn cp v dd gnd pes1 scl_source sda_source hpd_source rext gnd ddet pes0 v dd gnd in_d4+ in_d4 ? v dd in_d3+ in_d3 ? gnd in_d2+ in_d2 ? v dd in_d1+ in_d1 ? gnd 002aae078 PTN3381Bbs 12 25 11 26 10 27 9 28 8 29 7 30 6 31 5 32 4 33 3 34 2 35 1 36 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 terminal 1 index area transparent top view table 2. pin description symbol pin type description oe_n, in_dx and out_dx signals oe_n 25 3.3 v low-voltage cmos single-ended input output enable and power saving function for high-speed differential level shifter path. when oe_n = high: in_dx termination = high-impedance out_dx outputs = high-impedance; zero output current when oe_n = low: in_dx termination = 50 out_dx outputs = active in_d4+ 48 self-biasing differential input low-swing differential input from display source with pci express electrical signalling. in_d4+ makes a differential pair with in_d4 ? . the input to this pin must be ac coupled externally.
PTN3381B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 15 october 2010 7 of 30 nxp semiconductors PTN3381B fully integrated hdmi/dvi level shifter in_d4 ? 47 self-biasing differential input low-swing differential input from display source with pci express electrical signalling. in_d4 ? makes a differential pair with in_d4+. the input to this pin must be ac coupled externally. in_d3+ 45 self-biasing differential input low-swing differential input from display source with pci express electrical signalling. in_d3+ makes a differential pair with in_d3 ? . the input to this pin must be ac coupled externally. in_d3 ? 44 self-biasing differential input low-swing differential input from display source with pci express electrical signalling. in_d3 ? makes a differential pair with in_d3+. the input to this pin must be ac coupled externally. in_d2+ 42 self-biasing differential input low-swing differential input from display source with pci express electrical signalling. in_d2+ makes a differential pair with in_d2 ? . the input to this pin must be ac coupled externally. in_d2 ? 41 self-biasing differential input low-swing differential input from display source with pci express electrical signalling. in_d2 ? makes a differential pair with in_d2+. the input to this pin must be ac coupled externally. in_d1+ 39 self-biasing differential input low-swing differential input from display source with pci express electrical signalling. in_d1+ makes a differential pair with in_d1 ? . the input to this pin must be ac coupled externally. in_d1 ? 38 self-biasing differential input low-swing differential input from display source with pci express electrical signalling. in_d1 ? makes a differential pair with in_d1+. the input to this pin must be ac coupled externally. out_d4+ 13 tmds differential output hdmi compliant tmds output. out_d4+ makes a differential pair with out_d4 ? . out_d4+ is in phase with in_d4+. out_d4 ? 14 tmds differential output hdmi compliant tmds output. out_d4 ? makes a differential pair with out_d4+. out_d4 ? is in phase with in_d4 ? . out_d3+ 16 tmds differential output hdmi compliant tmds output. out_d3+ makes a differential pair with out_d3 ? . out_d3+ is in phase with in_d3+. out_d3 ? 17 tmds differential output hdmi compliant tmds output. out_d3 ? makes a differential pair with out_d3+. out_d3 ? is in phase with in_d3 ? . out_d2+ 19 tmds differential output hdmi compliant tmds output. out_d2+ makes a differential pair with out_d2 ? . out_d2+ is in phase with in_d2+. out_d2 ? 20 tmds differential output hdmi compliant tmds output. out_d2 ? makes a differential pair with out_d2+. out_d2 ? is in phase with in_d2 ? . out_d1+ 22 tmds differential output hdmi compliant tmds output. out_d1+ makes a differential pair with out_d1 ? . out_d1+ is in phase with in_d1+. out_d1 ? 23 tmds differential output hdmi compliant tmds output. out_d1 ? makes a differential pair with out_d1+. out_d1 ? is in phase with in_d1 ? . hpd and ddc signals hpd_sink 30 5 v cmos single-ended input 0 v to 5 v (nominal) input signal. this signal comes from the dvi or hdmi sink. a high value indicates that the sink is connected; a low value indicates that the sink is disconnected. hpd_sink is pulled down by an integrated 200 k pull-down resistor. hpd_source 7 3.3 v cmos single-ended output 0 v to 3.3 v (nominal) output signal. this is level-shifted version of the hpd_sink signal. scl_source 9 single-ended 3.3 v open-drain ddc i/o 3.3 v source-side ddc clock i/o. pulled up by external termination to 3.3 v. sda_source 8 single-ended 3.3 v open-drain ddc i/o 3.3 v source-side ddc data i/o. pulled up by external termination to 3.3 v. table 2. pin description ?continued symbol pin type description
PTN3381B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 15 october 2010 8 of 30 nxp semiconductors PTN3381B fully integrated hdmi/dvi level shifter [1] hvqfn48 package supply ground is connect ed to both gnd pins and exposed center pad. gnd pins and the exposed center pad must be connected to supply ground for proper device operation. for enhanc ed thermal, electrical, and board level performance, the e xposed pad needs to be soldered to the board using a corresponding t hermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the pcb in the thermal pad region. [2] a ceramic capacitor with esr < 100 m is recommended and should be placed close to the pin(s). scl_sink 28 single-ended 5 v open-drain ddc i/o 5 v sink-side ddc clock i/o. pulled up by external termination to 5 v. provides rise time accelerati on for low-to-high transitions. sda_sink 29 single-ended 5 v open-drain ddc i/o 5 v sink-side ddc data i/o. pulled up by external termination to 5 v. provides rise time accelerati on for low-to-high transitions. ddc_en 32 3.3 v cmos input enables the ddc buffer and level shifter. when ddc_en = low, buffer/level shifter is disabled. when ddc_en = high, buffer and level shifter are enabled. supply and ground v dd 2, 11, 15, 21, 26, 33, 40, 46 3.3 v dc supply supply voltage; 3.3 v 10 %. gnd [1] 1, 5, 12, 18, 24, 27, 31, 37, 43 ground supply ground. all gnd pins must be connected to ground for proper operation. feature control signals rext 6 analog i/o current sense port used to provide an accurate current reference for the differential outputs out_dx. for best output voltage swing accuracy, use of a 10 k resistor (1 % tolerance) from this terminal to gnd is recommended. may also be left open-circuit or tied to either v dd or gnd. see section 7.2 for details. ddet 4 3.3 v input dongle detect enable input. when high, the dongle detect function via i 2 c is active. when low, the dongle detect function will not respond to an i 2 c-bus command. must be tied to gnd or v dd either directly or via a resistor. note that this pin may not be left open-circuit. when used in an hdmi dongle, this pin must be tied high for correct operation in accordance with displayport interoperability guidelines. when used in a dvi dongle, this pin must be tied low. pes1 10 3.3 v cmos input programming pins to activa te the pre-emphasis feature of the tmds differential outputs. see section 7.3 for details. must be tied either to gnd or v dd either directly or via a resistor (< 1 k ). to disable pre-emphasis, connect both to gnd (pes[1:0] = 00b). pes[1:0] = 11b is reserved for testing purposes and should not be used in normal application. note that these pins may not be left open-circuit. pes0 3 3.3 v cmos input voltage regulator terminals cp 36 analog high-voltage positive terminal for the voltage regulator external capacitor. [2] cn 35 analog high-voltage negative terminal for the voltage regulator external capacitor. [2] v5out 34 power output 5 v regulated output from the integrated voltage regulator. [2] table 2. pin description ?continued symbol pin type description
PTN3381B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 15 october 2010 9 of 30 nxp semiconductors PTN3381B fully integrated hdmi/dvi level shifter 7. functional description refer to figure 2 ? functional diagram of PTN3381B ? . the PTN3381B level shifts four lanes of low-swing ac-coupled differential input signals to dvi and hdmi compliant open-drain current-steer ing differential output signals, up to 1.65 gbit/s per lane. speed of operation an d cable length drive may be extended (by using the programmable pre-emphasis feature) to up to 2.25 gbit/s per lane. it has integrated 50 termination resistors for ac-coupled differential input signals. an enable signal oe_n can be used to turn off the tm ds inputs and outputs, thereby minimizing power consumption. the tmds outputs are back- power safe to disallo w current flow from a powered sink while the PTN3381B is unpowered. the PTN3381B's ddc channel prov ides active level shifting and buffering, allowing 3.3 v source-side termination and 5 v sink-side termination. the sink-side ddc ports are equipped with a rise time accelerator enab ling drive of long cables or high bus capacitance. this enables the system designer to isolate bus capacitance to meet hdmi ddc version 1.3a distance specification. furthermore, the ddc channel is augmented with an i 2 c-bus slave rom device that provides optional hdmi dongle detect response, which can be enabled by dongle detect signal ddet. the PTN3381B offers back-power safe sink-side i/os to disallow backdrive cu rrent from the ddc clock and data lines when power is off or when ddc is not enabled. an enable signal dcc_en enables the ddc level shifter block. remark: when used in an hdmi dongle, the ddet function must be enabled for correct operation in accordance with di splayport interoperability guid elines. when used in a dvi dongle, the ddet function must be disabled. the PTN3381B also provides voltage transl ation for the hot plug detect (hpd) signal from 0 v to 5 v on the sink side to 0 v to 3.3 v on the source side. PTN3381B includes an onboard 5 v dc regulator, designed to provide the required 5 v power supply to the dvi or hdmi connector, thereby eliminating the need for a separate external regulator. the onboard regulator needs only two external capacitors to operate, and its output is active whenever a valid 3.3 v is applied to the PTN3381B v dd pins. the back drive protection on 5 v output prevents back-drive current fr om 5 v output to the input supply. the short-circuit protection limits current flowing through the supply, and the overcurrent protection prevents overload conditions at the charge pump output. the PTN3381B does not re-time any data. it contains no state machines except for the ddc/i 2 c-bus block. no inputs or outputs of the device are latched or clocked. because the PTN3381B acts as a transparent level shifter, no reset is required.
PTN3381B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 15 october 2010 10 of 30 nxp semiconductors PTN3381B fully integrated hdmi/dvi level shifter 7.1 enable and disable features PTN3381B offers different ways to enable or di sable functionality, using the output enable (oe_n), and ddc enable (ddc_en) inputs. wh enever the PTN3381B is disabled, the device will be in standby mo de and power consumption will be minimal; otherwise the PTN3381B will be in active mode and power consumption will be nominal. these two inputs each affect the operation of PTN3381B differently: oe_n controls the tmds channels, ddc_en affects only the ddc channe l, and hpd_sink does not affect either of the channels. the following sections and truth table describe their detailed operation. 7.1.1 hot plug detect the hpd channel of PTN3381B functions as a level-shifting buffer to pass the hpd logic signal from the display sink device (via inpu t hpd_sink) on to the display source device (via output hpd_source). the output logic state of hpd_source output always follows the logic state of input hpd_sink, regardless of whether the device is in active or standby mode. 7.1.2 output enable function (oe_n) when input oe_n is asserted (active low), the in_dx and out_dx signals are fully functional. input termination resistors are enabled and the internal bias circuits are turned on. when oe_n is de-asserted (inactive high), the out_dx outputs are in a high-impedance state and drive zero output cu rrent. the in_dx input buffers are disabled and in_dx termination is disabled . power consumption is minimized. remark: note that oe_n signal level has no influence on the hpd_sink input, hpd_source output, or the scl and sda level shifters. a transition from high to low at oe_n may disable the ddc channel for up to 20 s. 7.1.3 ddc channel enable function (ddc_en) the ddc_en pin is active high and can be used to isolate a badly behaved slave. when ddc_en is low, the ddc channel is turned off. the ddc_en input should never change state during an i 2 c-bus operation. note that disabling ddc_en during a bus operation may hang the bus, while enabling ddc_en during bus traffic would corrupt the i 2 c-bus operation. hence, ddc_en should only be toggled while the bus is idle. (see i 2 c-bus specification).
PTN3381B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 15 october 2010 11 of 30 nxp semiconductors PTN3381B fully integrated hdmi/dvi level shifter 7.1.4 enable/disable truth table [1] a high level on input oe_n disables only the tmds channels. [2] a low level on input ddc_en disables only the ddc channel. [3] out_dx channels ?enabled? means outputs out_dx toggling in accordance with in_dx differential input voltage switching. [4] ddc channel ?enabled? means sda_sink is connected to sda_source and scl_sink is connected to scl_source. [5] the hpd_source output logic state always follows the hpd_sink input logic state. table 3. hpd_sink, oe_n and ddc_en enabling truth table inputs channels mode hpd_sink oe_n [1] ddc_en [2] in_dx out_dx [3] ddc [4] hpd_source [5] low low low 50 termination to v rx(bias) enabled high-impedance low active; ddc disabled low low high 50 termination to v rx(bias) enabled sda_sink connected to sda_source and scl_sink connected to scl_source low active; ddc enabled low high low high-impedance high-impedance; zero output current high-impedance low standby low high high high-impedance high-impedance; zero output current sda_sink connected to sda_source and scl_sink connected to scl_source low standby; ddc enabled high low low 50 termination to v rx(bias) enabled high-impedance high active; ddc disabled high low high 50 termination to v rx(bias) enabled sda_sink connected to sda_source and scl_sink connected to scl_source high active; ddc enabled high high low high-impedance high-impedance; zero output current high-impedance high standby high high high high-impedance high-impedance; zero output current sda_sink connected to sda_source and scl_sink connected to scl_source high standby; ddc enabled
PTN3381B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 15 october 2010 12 of 30 nxp semiconductors PTN3381B fully integrated hdmi/dvi level shifter 7.2 analog current reference the rext pin (pin 6) is an analog current sense port used to provide an accurate current reference for the differential outputs out_dx. for best output voltage swing accuracy, use of a 10 k resistor (1 % tolerance) connect ed between this terminal and gnd is recommended. if an external 10 k ? 1 % resistor is not used, this pi n can be left open-circuit, or connected to gnd or v dd , either directly (0 ) or using pull-up or pull-down resistors of value less than 10 k . in any of these cases, the out put will function normally but at reduced accuracy over voltage and temperatur e of the following parameters: output levels (v ol ), differential output voltage swing, and rise and fall time accuracy. 7.3 programmable pre-emphasis PTN3381B includes an optional programmable pre-emphasis feature, allowing adaptor or motherboard pcb designers to extend speed per formance or support longer cable drive. the pre-emphasis feature, when enabled, add s a selectable amount of pre-emphasis to each bit transition by injecting a momentary current pulse (typically 200 ps to 400 ps long) to help overcome cable or trace losses. pre-emphasis is not needed for normal hdmi operation at speeds below 1.65 gbit/s and is not required to meet eye diagram compliance. at the user's discretion, it can be enabled in order to provide additional signal boost in difficult or lossy signaling environments such as long cables or lossy media. it should be noted that by enabling pre-emphasis, in addition to the ac effect of the pre-emphasis pulse on the signal transition, al so a constant dc current is added in order to provide the necessary he adroom, which will affect v oh and v ol static levels. this should be taken into account when designing for hdmi or dvi single-ended (dc) voltage compliance. for full hdmi or dvi complianc e in normal applications, the default mode (pre-emphasis off) is recommended. the pre-emphasis feature is programmed by means of two cmos input pins, pes1 and pes0, according to table 4 : [1] should not be used in normal application. 7.4 backdrive current protection the PTN3381B is designed for backdrive prevention on all sink-side tmds outputs, sink-side ddc i/os and the hpd_sink input. this supports user scenarios where the display is connected and powered, but the pt n3381b is unpowered. in these cases, the PTN3381B will sink no more than a negligible amount of leakage current, and will block the display (sink) termination network from driving the power supply of the PTN3381B or that of the inactive dvi or hdmi source. table 4. PTN3381B pre-emphasis logic table pes1 (pin 10) pes0 (pin 3) level 0 0 0 db (default) 0 1 3.5 db (150 %) 106db (200%) 1 1 test mode [1]
PTN3381B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 15 october 2010 13 of 30 nxp semiconductors PTN3381B fully integrated hdmi/dvi level shifter 7.5 active ddc buf fer with rise time accelerator the PTN3381B ddc channel, besides providing 3. 3 v to 5 v level shifting, includes active buffering and rise time acceleration which allows up to 18 meters bus extension for reliable ddc applications. while retaining a ll the operating modes and features of the i 2 c-bus system during the level shifts, it permits extension of the i 2 c-bus by providing bidirectional buffering for both the data (sda) and the clock (scl) line as well as the rise time accelerator on the sink-side port (scl_sink and sda_sink) enabling the bus to drive a load up to 1400 pf or distance of 18 m on the sink-side port, and 400 pf on the source-side port (scl_source and sca_so urce). using the PTN3381B for dvi or hdmi level shifting enables the system designer to isolate bus capacitance to meet hdmi ddc version 1.3 distance specification. the sda and scl pins are overvoltage tolerant and are high-impedance wh en the PTN3381B is unpowered or when ddc_en is low. PTN3381B has rise time accelerators on the sink-side port (scl_sink and sda_sink) only. during positive bus transitions on the sink-side port, a current source is switched on to quickly slew the scl_sink and sda_ sink lines high once the 5 v ddc bus v il threshold level of around 1.5 v is exceeded, and turns off as the 5 v ddc bus v ih threshold voltage of approximately 3.5 v is approached. 7.6 i 2 c-bus based hdmi dongle detection the PTN3381B includes an on-board i 2 c-bus slave rom which provides a means to detect the presence of an hdmi dongle by the system through the ddc channel, accessible via ports sda_source and scl_so urce. this allows system vendors to detect hdmi dongle presence through the already available ddc/i 2 c-bus port using a predetermined bus sequence. please see section 8 for more information. for the i 2 c-bus hdmi dongle detect function to be active, input pin ddet (dongle detect) should be tied high. when ddet is low, the PTN3381B will not respond to an i 2 c-bus command. when used in an hdmi dongle, the ddet function must be enabled for correct operation in accordan ce with displayport interoperability guide lines. when used in a dvi dongle, the ddet function must be disabled. the hdmi dongle detection is accomplish ed by accessing the PTN3381B on-board i 2 c-bus slave rom using a simple sequential i 2 c-bus read operation as described below. 7.6.1 slave address r=1; w =0 fig 4. PTN3381B slave address 002aad34 0 1 0 0 0 0 0 0 r/w slave address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
PTN3381B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 15 october 2010 14 of 30 nxp semiconductors PTN3381B fully integrated hdmi/dvi level shifter 7.6.2 read operation the slave device ad dress of PTN3381B is 80h. pt n3381b will respond to a read command to slave address 81h (PTN3381B will respond with an ack to a write command to address 80h). fo llowing the read command, the PTN3381B will respond with the contents of its internal rom, as a sequ ence of 16 bytes, for as long as the master continues to issue clock edges with an acknowledge after each byte. the 16-byte sequence represents the ?dp-hdmi adapto r? symbol converted to ascii and is documented in ta b l e 5 . the PTN3381B auto-increments its internal rom address pointer (0h through fh) as long as it continues to receive clock edges from the master with an acknowledge after each byte. if the master continues to issue clock edges past the 16 th byte, the PTN3381B will respond with a data byte of ffh. if the mast er does not acknowledge a received byte, the PTN3381B internal address po inter will be reset to 0 and a new read sequence should be started by the master. access to the 16-byt e is by sequential read only as described above; there is no random-access possib le to any specific byte in the rom. remark: if the slave does not acknowledge the above transaction sequence, the entire sequence should be retried by the source. table 5. displayport - hdmi ad aptor detection rom content internal pointer offset (hex) 0 1 2 3 4 5 6 7 8 9 a b c d e f data (hex) 44 50 2d 48 44 4d 49 20 41 44 41 50 54 4f 52 04 table 6. hdmi dongle detect transaction sequence outline phase i 2 c transaction transmitting bit status 7 6 5 4 3 2 1 r/w master slave 1 start master optional - 2 write command master 1000000 0 optional - 3 acknowledge slave - mandatory 4 word address offset master word address offset data byte optional - 5 acknowledge slave - mandatory 6 stop master optional - 7 start master mandatory - 8 read command master 1 0 0 0 0 0 0 1 mandatory - 9 acknowledge slave - mandatory 10 read data slave data byte at offset 0 - mandatory 11 acknowledge master mandatory - 12 read data slave data byte at offset 1 - mandatory 13 : : - - :: : - - 40 read data slave data byte at offset 15 - mandatory 41 not acknowledge master mandatory - 42 stop master mandatory -
PTN3381B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 15 october 2010 15 of 30 nxp semiconductors PTN3381B fully integrated hdmi/dvi level shifter 7.7 characteristics of the i 2 c-bus the i 2 c-bus is for 2-way, 2-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up re sistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. 7.7.1 bit transfer one data bit is transferred during each clock phase. the data on the sda line must remain stable during the high period of the cl ock pulse as changes in the data line at this time will be interpreted as control signals (see figure 5 ). 7.7.2 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line, while the clock is high is defined as the start condition (s). a low-to-high transition of the data line while the clock is high is defined as the stop condition (p). see figure 6 . 7.7.3 system configuration an i 2 c-bus device generating a message is a ?transmitter?, a devic e receiving is the ?receiver?. the device that controls the messa ge is the ?master? and the devices which are controlled by the master are the ?slaves?. see figure 7 . fig 5. bit transfer mba60 7 data line stable; data valid change of data allowed sda scl fig 6. definition of start and stop conditions. mba60 8 sda scl p stop condition s start condition
PTN3381B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 15 october 2010 16 of 30 nxp semiconductors PTN3381B fully integrated hdmi/dvi level shifter 7.7.4 acknowledge the number of data bytes transferred betwe en the start and the stop conditions from transmitter to receiver is not limited. each byte of eight bits is followed by one acknowledge bit. the acknowledge bit is a high level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must gen erate an acknowledge af ter the reception of each byte. also, a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transm itter. the device that acknowledges has to pull down the sda line during the acknowledge cl ock pulse so that the sda line is stable low during the high period of the acknowledge related clock pulse, set-up and hold times must be taken into account. a master receiver must signal an end of da ta to the transmitter by not generating as acknowledge on the last byte that has been cloc ked out of the slave. in this event, the transmitter must leave the data line high to enable the master to generate a stop condition. fig 7. system configuration 002aaa38 1 master transmitter/ receiver slave receiver slave transmitter/ receiver master transmitter master transmitter/ receiver sda scl fig 8. acknowledgement on the i 2 c-bus 002aaa98 7 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master
PTN3381B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 15 october 2010 17 of 30 nxp semiconductors PTN3381B fully integrated hdmi/dvi level shifter 8. application design-in information 8.1 dongle or cable adaptor detect discovery mechanism the PTN3381B supports the source-side dongle detect discovery mechanism described in vesa displayport inte roperability guide line version 1.1 . when a source-side cable adaptor is plugged into a multi-mode source device that supports multiple standards such as displayport, dvi and hdmi, a discovery mechanism is needed for the multi-mode source to confi gure itself for outputting displayport, dvi or hdmi compliant signals through the dongle or cable adaptor. the discovery mechanism ensures that a multi-mode sour ce device only sends either dvi or hdmi signals when a valid dvi or hdmi cable adaptor is present. the v esa interoperability guideline recommends that a multi-mode source to power up with both ddc and aux ch disabled. after init ialization, the source device can use a variety of mechanisms to decide whether a dongle or cable adaptor is present by detecting pin 13 on the displayport connector. depending on the voltage level detected at pin 13, the source configures itself either: ? as a dvi or hdmi source (see below paragraph for detection between dvi and hdmi), and enables d dc, while keeping aux ch disabled, or ? as a displayport source and enables aux ch, while keeping ddc disabled. the monitoring of the voltage level on pin 13 by a multi-mode source device is optional. a multi-mode source may also e.g. attempt an aux ch read transaction and, if the transaction fails, a ddc transaction to discover the pres ence/absence of a cable adaptor. furthermore, a source that supports both dvi and hdmi can discover whether a dvi or hdmi dongle or cable adaptor is present by using a variety of discovery procedures. one possible method is to check the voltage leve l of pin 14 of the displayport connector. pin 14 also carries cec signal used for hdmi. please note that other hdmi devices on the cec line may be momentarily pulling dow n pin 14 as a part of cec protocol. the vesa interoperability guideline recommends that a multi-mode source should distinguish a source-side hdmi cable adaptor from a dvi cable adaptor by checking the ddc buffer id as described in section 7.6 ? i 2 c-bus based hdmi dongle detection ? . while it is optional for a multi-mode source to use the i 2 c-bus based hdmi dongle detection mechanism, it is mandatory for hdmi dongle or cable adaptor to respond to the i 2 c-bus read command described in section 7.7 . the PTN3381B provides an integrated i 2 c-bus slave rom to support this mandatory hdmi dongle detect mechanism for hdmi dongles. for a displayport-to-hdmi source-side dongle or cable adaptor, ddet must be tied high to enable the i 2 c-based hdmi dongle detection response function of PTN3381B. for a displayport-to-dvi sink-side do ngle or cable adaptor, ddet must be tied low to disable the function.
PTN3381B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 15 october 2010 18 of 30 nxp semiconductors PTN3381B fully integrated hdmi/dvi level shifter 9. limiting values [1] human body model: ansi/eos/esd-s5.1-1994, standard for esd sensitivity testing, human body model - component level; electrostatic disc harge association, rome, ny, usa. [2] charged device model: ansi/eos/esd-s5.3-1-1999, stand ard for esd sensitivity testing, charged device model - component level; electrostatic discharge association, rome, ny, usa. 10. recommended operating conditions [1] input signals to these pins must be ac-coupled. [2] operation without external reference resistor is possible but will result in reduced output voltage swing accuracy. for details, see section 7.2 . [3] a ceramic capacitor with esr < 100 m is recommended and should be pl aced close to the pin(s). table 7. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage (3.3 v) ? 0.3 +4.6 v v i input voltage 3.3 v cmos inputs ? 0.3 v dd +0.5 v 5.0 v cmos inputs ? 0.3 6.0 v r l load resistance 5 v regulator output 25 - t stg storage temperature ? 65 +150 c v esd electrostatic discharge voltage hbm [1] - 4000 v cdm [2] - 1000 v table 8. recommended operating conditions symbol parameter conditions min typ max unit v dd supply voltage 3.0 3.3 3.6 v v i input voltage 3.3 v cmos inputs 0 - 3.6 v 5.0 v cmos inputs 0 - 5.5 v v i(av) average input voltage in_dn+, in_dn ? inputs [1] -0 -v r ref(ext) external reference resistance connected between pin rext (pin 6) and gnd [2] -10 1% - k i load load current 5 v regulator output - - 75 ma c o(reg) regulator output capacitance external capacitor on pin v5out [3] -1 - f c reg(ext) external regulator capacitance from pin cp to pin cn [3] -330 -nf t amb ambient temperature operating in free air ? 40 - +85 c
PTN3381B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 15 october 2010 19 of 30 nxp semiconductors PTN3381B fully integrated hdmi/dvi level shifter 10.1 current consumption 11. characteristics 11.1 differential inputs [1] ui (unit interval) = t bit (bit time). [2] ui is determined by the display mode. nominal bit rate range s from 250 mbit/s to 1.65 gbit/s per lane. nominal ui at 1.65 gbit/s = 606 ps. [3] v rx_diffp-p = 2 | v rx_d+ ? v rx_d ? | . applies to in_dx signals. [4] v i(cm)m(ac) = | v rx_d+ +v rx_d ? | /2 ? v rx(cm) . v rx(cm) = dc (avg) of | v rx_d+ +v rx_d ? | /2. [5] intended to limit power-up stress on chip set?s pcie output buffers. [6] differential inputs will switch to a high-impedance state when oe_n is high. table 9. current consumption symbol parameter conditions min typ max unit i dd supply current oe_n = 0; active mode no load 10 30 50 ma with 75 ma load - 200 300 ma oe_n = 1 and ddc_en = 0; standby mode; no load --5ma table 10. differential input characteristics for in_dx signals symbol parameter conditions min typ max unit ui unit interval [1] [2] 600 - 4000 ps v rx_diffp-p differential input peak-to-peak voltage [3] 0.175 - 1.200 v t rx_eye receiver eye time minimum eye width at in_dx input pair 0.8 - - ui v i(cm)m(ac) peak common-mode input voltage (ac) includes all frequencies above 30 khz [4] --100mv z rx_dc dc input impedance 40 50 60 v rx(bias) bias receiver voltage [5] 1.0 1.2 1.4 v z i(se) single-ended input impedance inputs in high-impedance state [6] 100 - - k
PTN3381B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 15 october 2010 20 of 30 nxp semiconductors PTN3381B fully integrated hdmi/dvi level shifter 11.2 differential outputs the level shifter?s differential outputs are designed to meet hdmi version 1.3 and dvi version 1.0 specifications. [1] v tt is the dc termination voltage in the hdmi or dvi sink. v tt is nominally 3.3 v. [2] the open-drain output pulls down from v tt . [3] swing down from tmds termination voltage (3.3 v 10 %). [4] this differential skew budget is in addition to the skew presented between in_dn+ and in_dn ? paired input pins. [5] this lane-to-lane skew budget is in additi on to skew between differential input pairs. [6] jitter budget for differential signals as they pass through the level shifter. 11.3 hpd_sink input , hpd_source output [1] low-speed input changes state on cable plug/unplug. [2] time from hpd_sink changing state to hpd_source changing state. includes hpd_source rise/fall time. [3] time required to transition from v oh to v ol or from v ol to v oh . [4] guarantees hpd_sink is low when no display is plugged in. table 11. differential output char acteristics for out_dx signals symbol parameter conditions min typ max unit v oh(se) single-ended high-level output voltage pes[1:0] = 00b [1] v tt ? 0.01 v tt v tt +0.01 v v ol(se) single-ended low-level output voltage pes[1:0] = 00b [2] v tt ? 0.60 v tt ? 0.50 v tt ? 0.40 v v o(se) single-ended output voltage variation logic 1 and logic 0 state applied respectively to differential inputs in_dn; r ref(ext) connected; see ta b l e 8 [3] 400 500 600 mv i oz off-state output current single-ended - - 10 a t r rise time 20 % to 80 % 75 - 180 ps t f fall time 80 % to 20 % 75 - 180 ps t sk skew time intra-pair [4] --10ps inter-pair [5] --250ps t jit jitter time jitter contribution [6] --10ps table 12. hpd characteristics symbol parameter conditions min typ max unit v ih high-level input voltage hpd_sink [1] 2.0 5.0 5.3 v v il low-level input voltage hpd_sink 0 - 0.8 v i li input leakage current hpd_sink - - 15 a v oh high-level output voltage hpd_source 2.5 - v dd v v ol low-level output voltage hpd_source 0 - 0.2 v t pd propagation delay from hpd_sink to hpd_source; 50 % to 50 % [2] --200ns t t transition time hpd_source rise/fall; 10 % to 90 % [3] 1 - 20 ns r pd pull-down resistance hpd_sink input pull-down resistor [4] 100 200 300 k
PTN3381B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 15 october 2010 21 of 30 nxp semiconductors PTN3381B fully integrated hdmi/dvi level shifter 11.4 oe_n, ddc_en and ddet inputs [1] measured with input at v ih maximum and v il minimum. 11.5 ddc characteristics [1] v cc1 is the pull-up voltage for ddc source. [2] v cc2 is the pull-up voltage for ddc sink. table 13. oe_n, ddc_en and ddet input characteristics symbol parameter conditions min typ max unit v ih high-level input voltage 2.0 - v v il low-level input voltage - 0.8 v i li input leakage current oe_n pin [1] --10 a table 14. ddc characteristics symbol parameter conditions min typ max unit input and output scl_ source and sda_source; v cc1 = 3.0v to 3.6v [1] v ih high-level input voltage 0.7v cc1 -3.6 v v il low-level input voltage ? 0.5 - +0.3v cc1 v v ilc contention low-level input voltage ? 0.5 0.4 - v i li input leakage current v i =3.6v - - 10 a i il low-level input current v i =0.2v - - 10 a v ol low-level output voltage i ol =100 a or 6 ma 0.47 0.52 0.6 v v ol ? v ilc difference between low-level output and low-level input voltage contention guaranteed by design - - 70 mv c io input/output capacitance v i =3v or 0v; v dd =3.3v - 6 7 pf v i = 3 v or 0 v; v dd =0v - 6 7 pf input and output sda_ sink and scl_sink; v cc2 = 4.5v to 5.5v [2] v ih high-level input voltage 0.7v cc2 -5.5 v v il low-level input voltage ? 0.5 - +1.5 v i li input leakage current v i =5.5v - - 10 a i il low-level input current v i =0.2v - - 10 a v ol low-level output voltage i ol =6ma - 0.1 0.2 v c io input/output capacitance v i =3v or 0v; v dd =3.3v - - 7 pf v i = 3 v or 0 v; v dd =0v - 6 7 pf i trt(pu) transient boosted pull-up current v cc2 =4.5v; slew rate = 1.25 v/ s -6-ma
PTN3381B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 15 october 2010 22 of 30 nxp semiconductors PTN3381B fully integrated hdmi/dvi level shifter 11.6 5 v dc regulator characteristics [1] recommend low esr ceramic output capacitor of 2 f to reduce the output ripple. table 15. 5 v dc regulator characteristics symbol parameter conditions min typ max unit v dd supply voltage 3.0 3.3 3.6 v v o output voltage 5 v regulator output 4.7 5 5.3 v i load load current 5 v regulator output - - 75 ma i o(sc) short-circuit output current 100 150 200 ma i bckdrv backdrive current 5 v regulator output - - 10 a v o(ripple)(p-p) peak-to-peak ripple output voltage c o(reg) =1 f [1] - 250 400 mv efficiency i load >10ma 707580%
PTN3381B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 15 october 2010 23 of 30 nxp semiconductors PTN3381B fully integrated hdmi/dvi level shifter 12. package outline fig 9. package outline sot619-1 (hvqfn48) 0.5 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 7.1 6.9 d h 5.25 4.95 y 1 7.1 6.9 5.25 4.95 e 1 5.5 e 2 5.5 0.30 0.18 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot619-1 mo-220 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot619 -1 h vqfn48: plastic thermal enhanced very thin quad flat package; no leads; 4 8 terminals; body 7 x 7 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 13 24 48 37 36 25 12 1 x d e c b a e 2 01-08-08 02-10-18 terminal 1 index area terminal 1 index area 1/2 e 1/2 e a c c b v m w m e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1)
PTN3381B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 15 october 2010 24 of 30 nxp semiconductors PTN3381B fully integrated hdmi/dvi level shifter 13. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 13.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 13.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities
PTN3381B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 15 october 2010 25 of 30 nxp semiconductors PTN3381B fully integrated hdmi/dvi level shifter 13.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 10 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and coolin g down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 1 6 and 17 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 10 . table 16. snpb eutectic process (from j-std-020c) package thickness (mm) package reflow temperature ( c) volume (mm 3 ) < 350 350 < 2.5 235 220 2.5 220 220 table 17. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
PTN3381B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 15 october 2010 26 of 30 nxp semiconductors PTN3381B fully integrated hdmi/dvi level shifter for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . 14. abbreviations msl: moisture sensitivity level fig 10. temperature profiles for large and small components 001aac84 4 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 18. abbreviations acronym description cdm charged-device model cec consumer electronics control ddc data display channel dvi digital visual interface esd electrostatic discharge esr equivalent series resistance hbm human body model hdmi high-definition multimedia interface hpd hot plug detect i 2 c-bus inter-ic bus i/o input/output tmds transition minimized differential signaling vesa video electronic st andards association
PTN3381B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 15 october 2010 27 of 30 nxp semiconductors PTN3381B fully integrated hdmi/dvi level shifter 15. revision history table 19. revision history document id release date data sheet status change notice supersedes PTN3381B v.2 20101015 product data sheet - PTN3381B v.1 PTN3381B v.1 20100930 product data sheet - -
PTN3381B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 15 october 2010 28 of 30 nxp semiconductors PTN3381B fully integrated hdmi/dvi level shifter 16. legal information 16.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 16.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 16.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interrupt ion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification.
PTN3381B all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 15 october 2010 29 of 30 nxp semiconductors PTN3381B fully integrated hdmi/dvi level shifter non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive s pecifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully in demnifies nxp semi conductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive appl ications beyond nxp semiconductors? standard warranty and nxp semicond uctors? product specifications. 16.4 licenses 16.5 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 17. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com purchase of nxp ics with hdmi technology use of an nxp ic with hdmi technology in equipment that complies with the hdmi standard requires a license from hdmi licensing llc, 1060 e. arques avenue suite 100, sunnyvale ca 94085, usa, e-mail: admin@hdmi.org .
nxp semiconductors PTN3381B fully integrated hdmi/dvi level shifter ? nxp b.v. 2010. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 15 october 2010 document identifier: PTN3381B please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 18. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 3 2.1 high-speed tmds level shifting . . . . . . . . . . . . 3 2.2 ddc level shifting . . . . . . . . . . . . . . . . . . . . . . . 3 2.3 hdmi dongle detect support . . . . . . . . . . . . . . . 3 2.4 hpd level shifting . . . . . . . . . . . . . . . . . . . . . . . 3 2.5 5 v dc voltage regulator . . . . . . . . . . . . . . . . . 3 2.6 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 ordering information . . . . . . . . . . . . . . . . . . . . . 4 5 functional diagram . . . . . . . . . . . . . . . . . . . . . . 5 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 functional description . . . . . . . . . . . . . . . . . . . 9 7.1 enable and disable features . . . . . . . . . . . . . . 10 7.1.1 hot plug detect . . . . . . . . . . . . . . . . . . . . . . . 10 7.1.2 output enable function (oe_n) . . . . . . . . . . . 10 7.1.3 ddc channel enable function (ddc_en). . . . 10 7.1.4 enable/disable truth table . . . . . . . . . . . . . . . . 11 7.2 analog current reference . . . . . . . . . . . . . . . . 12 7.3 programmable pre-emphasis . . . . . . . . . . . . . 12 7.4 backdrive current protection . . . . . . . . . . . . . . 12 7.5 active ddc buffer with rise time accelerator . 13 7.6 i 2 c-bus based hdmi dongle detection . . . . . . 13 7.6.1 slave address . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.6.2 read operation . . . . . . . . . . . . . . . . . . . . . . . . 14 7.7 characteristics of the i 2 c-bus. . . . . . . . . . . . . 15 7.7.1 bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.7.2 start and stop conditions . . . . . . . . . . . . . 15 7.7.3 system configuration . . . . . . . . . . . . . . . . . . . 15 7.7.4 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 16 8 application design-in information . . . . . . . . . 17 8.1 dongle or cable adaptor detect discovery mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 18 10 recommended operating conditions. . . . . . . 18 10.1 current consumption . . . . . . . . . . . . . . . . . . . 19 11 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 19 11.1 differential inputs . . . . . . . . . . . . . . . . . . . . . . 19 11.2 differential outputs . . . . . . . . . . . . . . . . . . . . . 20 11.3 hpd_sink input, hpd_source output . . . . 20 11.4 oe_n, ddc_en and ddet inputs. . . . . . . . . 21 11.5 ddc characteristics . . . . . . . . . . . . . . . . . . . . 21 11.6 5 v dc regulator characteristics . . . . . . . . . . . 22 12 package outline. . . . . . . . . . . . . . . . . . . . . . . . 23 13 soldering of smd packages . . . . . . . . . . . . . . 24 13.1 introduction to soldering. . . . . . . . . . . . . . . . . 24 13.2 wave and reflow soldering. . . . . . . . . . . . . . . 24 13.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . 24 13.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . 25 14 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 26 15 revision history . . . . . . . . . . . . . . . . . . . . . . . 27 16 legal information . . . . . . . . . . . . . . . . . . . . . . 28 16.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 28 16.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 16.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 28 16.4 licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 16.5 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 29 17 contact information . . . . . . . . . . . . . . . . . . . . 29 18 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

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